Increasing a refresh period in a semiconductor memory device

ABSTRACT

In one method according to an embodiment of the invention, a reference bitline is biased and a refresh period of a DRAM cell is increased. In one example of such a method, biasing the reference bitline includes applying a predetermined bias voltage. In a memory device according to one embodiment of the invention, a bias circuit includes a bias capacitor connected to a bitline and configured and arranged to receive a bias signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application claims benefit of International Patent Application No.PCT/KR03/00051, filed Jan. 10, 2003, which claims benefit of U.S.Provisional Patent Application No. 60/346,897, filed Jan. 11, 2002, bothof these documents being incorporated herein by reference in theirentireties.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device; and,more particularly, to data storage in the semiconductor memory device.

BACKGROUND ART

Semiconductor random-access memories are widely used in electroniccomputing applications. For many applications, dynamic random accessmemory (DRAM) devices are preferred for such features as high storagedensity and low cost.

FIG. 1 shows a circuit diagram of a one-transistor DRAM cell. The cellincludes a cell capacitor C that stores a charge corresponding to a datavalue. Cell capacitor C is coupled to a bitline BL through afield-effect transistor (FET) M1, and the gate of FET M1 is connected toa wordline WL.

Before the cell is read, the inherent capacitance C_(BL) of bitline BLis precharged to a predetermined level. To retrieve the data valuestored in cell capacitor C, wordline WL is pulled high to activate FETM1. This action causes charge sharing between cell capacitor C andinherent capacitance C_(BL). This charge sharing causes the voltage onbitline BL to vary from the precharge level according to the chargestored in cell capacitor C. A sense amplifier (not shown) detects andamplifies the voltage change on bitline BL to retrieve and output thecorresponding data value.

One disadvantage of a DRAM cell as shown in FIG. 1 is that the level ofthe charge stored by cell capacitor C deteriorates over time (e.g.through leakage due to a nonideal dielectric). Once the charge level hasdeteriorated to the point where the sense amplifier can no longerproperly detect the corresponding voltage change on bitline BL, thestored data value is lost. Therefore, it is necessary to refresh thecharge stored in the cell capacitor from time to time.

When a DRAM cell is being refreshed, the stored data value cannot beaccessed and a new data value cannot be stored. Therefore, the need forrefresh activity imposes a limit on the performance of a memory systemthat includes DRAM devices. It is desirable to increase the periodbetween refresh operations (the “refresh period”) in order to reduce theimpact of this activity on memory system performance.

Increasing the refresh period may also reduce power consumption. Inorder to retain the information stored in its DRAM devices, for example,an electronic unit performs refresh operations even when the unit is notin active use. In the case of a handheld unit such as a cellulartelephone, a personal digital assistant, or a notebook computer, powerexpended in performing DRAM refresh may represent a significant portionof the unit's total standby power drain. By reducing the number ofrefresh operations that are performed over a given period of time,increasing the refresh period may reduce the standby power consumptionof the unit and help to extend the period over which such a unit mayremain in standby mode for a single battery charge.

One technique for achieving a longer period between refresh operationsis to increase the capacitance of cell capacitor C. However, thistechnique may include increasing the size of cell capacitor C, andundesirable effects of such an increase may include a reduction instorage density and/or a greatly increased circuit area.

Another technique for achieving a longer period between refreshoperations is to reduce the ratio of the capacitance of the bitline tothe capacitance of the cell capacitor. By increasing the magnitude ofthe voltage change on the bitline upon charge sharing, this techniquemay extend the period over which the charge on the cell capacitorremains detectable. Unfortunately, this technique may also includeincreasing the size of the cell capacitor. It is desirable to increasethe period between refresh operations in a DRAM device withoutincreasing the size of a cell capacitor.

SUMMARY

In a method according to one embodiment of the invention, a firstbitline and a second bitline are precharged. Charge sharing between acell capacitor and the precharged first bitline is permitted, and aselected one of the precharged bitlines is biased. For example, biasinga bitline may include reducing a potential of the bitline. Biasing abitline may also include applying a potential to a bias capacitorcoupled to the selected bitline. Subsequent to the charge sharing andthe biasing, a difference between the potentials of the bitlines of thefirst and second memory cells is sensed, where sensing the differencebetween the potentials may include amplifying the difference between thepotentials.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and aspects of the invention will become apparent from thefollowing description of the embodiments with reference to theaccompanying drawings, in which:

FIG. 1 is a schematic diagram of a one-transistor DRAM cell;

FIG. 2 is a block diagram of a device including a cell array, a senseamplifier, and a precharge circuit;

FIG. 3 is a schematic diagram of a precharge circuit;

FIG. 4 is a schematic diagram of a sense amplifier;

FIG. 5 is a schematic diagram of a circuit including a sense amplifier;

FIG. 6 is a timing diagram of a device as shown in FIG. 2;

FIG. 7 is a timing diagram of a device as shown in FIG. 2;

FIG. 8 is a block diagram of a device according to an embodiment of theinvention;

FIG. 9 is a timing diagram of a device as shown in FIG. 8;

FIG. 10 is a timing diagram of a device as shown in FIG. 8;

FIG. 11 is a block diagram of a device according to another embodimentof the invention;

FIG. 12 is a block diagram of two cell arrays;

FIG. 13 is a schematic diagram of an isolation circuit; and

FIG. 14 is a timing diagram of a device as shown in FIG. 11.

DETAILED DESCRIPTION

FIG. 2 shows a block diagram of a DRAM device that includes a cell array110, a sense amplifier 120, and a precharge circuit 130. Cell array 110includes two instances of the cell shown in FIG. 1: cell 1 comprisingFET M1 and cell capacitor C1, and cell 2 comprising FET M2 and cellcapacitor C2. In exemplary implementations, each of the cell capacitorsC1, C2 may be fabricated as a two-terminal capacitor or as a trenchcapacitor. In other implementations of a device as shown in FIG. 2, theseries connection of cell array 110, sense amplifier 120, and prechargecircuit 130 along bitline BL1, BL2 may occur in any order.

In an exemplary application of the device of FIG. 2, the ends of cellcapacitors C1, C2 opposite FETs M1, M2 are connected to a potentialhaving a value of Vdd/2. In such case a data value may be entered into acell by storing a voltage Vdd (for ‘high’ or data ‘1’) or a voltage Vss(for ‘low’ or data ‘0’) across the cell capacitor. In exemplaryimplementations, a difference between Vdd and Vss may be as great asthree, five, or nine volts or more or as little as one-and-one-halfvolts or one volt or less.

As mentioned above, the inherent capacitances of the bitlines areprecharged before selection of a cell for reading. FIG. 3 shows aschematic diagram for a precharge circuit 130 a suitable for use in adevice as shown in FIG. 2. This circuit includes three series-connectedN-channel FETs P1–P3 having one junction connected to each bitline andthe ends of the series connected to a precharging signal PC that has apotential of Vblp. In an exemplary application, Vblp has a value ofVdd/2. The gates of FETs. P1–P3 are connected together and to anactive-low precharge control signal P.

A precharge circuit as shown in FIG. 3 may also be referred to as anequalizer. Other types of precharge circuits as are known in the art mayalso be substituted as precharge circuit 130.

Upon charge sharing, a voltage change ΔV occurs on the correspondingbitline. Because the charge stored in the cell capacitor is very small(a capacitance of cell capacitor C may be less than one hundredfemtofarads), detection of the stored voltage level usually requiresamplification of ΔV. FIG. 4 shows a schematic diagram for a senseamplifier 120 a suitable for use in a device as shown in FIG. 2. Senseamplifier 120 a includes two P-channel FETs S1, S3 having theirseries-connected source-drain circuits connected across bitlines BL1,BL2 and their junction connected to an active-high enable signal SA-P.Sense amplifier 120 a also includes two N-channel FETs S2, S4 havingtheir series-connected source-drain circuits connected across bitlinesBL1, BL2 and their junction connected to an active-low enable signalSA-N. The gates of the pair of FETs that are connected to each bitlineare connected together and to the other bitline.

A sense amplifier circuit as shown in FIG. 4 may be characterized as twoCMOS inverters connected in opposite directions across bitlines BL1 andBL2. Such a circuit may also be viewed as one form of a latching senseamplifier. Other forms of latching sense amplifier circuits, and variousother types of sense amplifier circuits such as current-mirror senseamplifier circuits, are known in the art and may also be substituted assense amplifier 120.

The circuit of sense amplifier 120 a may also be modified as shown inFIG. 5. This modification includes a P-channel FET S5 having its gateconnected to enable signal SA-P, with one terminal of its source-draincircuit connected to Vdd and the other to the junction of the P-channelsource-drain circuits of FETs S1, S3. The modification also includes anN-channel FET S6 having its gate connected to enable signal SA-N, withone terminal of its source-drain circuit connected to Vss and the otherto the junction of the N-channel source-drain circuits of FETs S2, S4.

FIG. 6 shows a timing diagram of an exemplary application of a device asshown in FIG. 2 in a case where a high data value has been stored incell 1 of array 110. During standby mode of the DRAM device, controlsignal P of precharge circuit 130 has a high level, and the inherentcapacitances of bitlines BL1, BL2 are precharged to a potential Vblp.During active mode of the DRAM device, precharge control signal P ispulled low, causing bitlines BL1, BL2 to float. Cell 1 is then selectedby pulling wordline WL1 high, thus activating transistor M1.

Upon activation of transistor Ml, charge sharing occurs between cellcapacitor C1 and the (precharged) inherent capacitance of bitline BL1.As cell capacitor C1 stores a high data value in this example, thecharge sharing raises the voltage on bitline BL1 by ΔV as compared tothe voltage Vblp on the reference bitline BL2. Sense amplifier 120 isactivated by pulling enable signals SA-P and SA-N high and low,respectively, causing sense amplifier 120 to amplify the voltage levelson bitlines BL1, BL2 to Vdd and Vss, respectively.

FIG. 7 shows a timing diagram of an exemplary application of a device asshown in FIG. 2 in a case where a low data value has been stored in cell1 of array 110. As cell capacitor C1 stores a low data value in thisexample, charge sharing results in a decrease of the voltage on bitlineBL1 by ΔV as compared to the voltage Vblp on the reference bitline BL2.Upon activation, sense amplifier 120 amplifies the voltage levels onbitlines BL1, BL2 to Vss and Vdd, respectively.

As the charge level on a cell capacitor deteriorates, the voltage changeΔV produced on the bitline upon charge sharing decreases. If the voltagechange ΔV falls below the sense margin of sense amplifier 120, then thecharge level can no longer be distinguished (i.e. is no longer readableby the sense amplifier), and the stored data value is lost.

A cell capacitor as shown in FIG. 1 can typically maintain a low chargelevel (i.e. a charge level corresponding to a low voltage or data value)to a readable level over a longer period than it can maintain a highcharge level (i.e. a charge level corresponding to a high voltage ordata value) to a readable level. For example, a cell capacitor maymaintain a low charge level to a readable level for several seconds,while the same cell capacitor may maintain a high charge level to areadable level for only several hundred milliseconds or less—a disparityof roughly one order of magnitude.

It is impractical for the stored information to be known a priori, andrefresh operations in a memory system including DRAM devices are usuallydesigned to occur periodically, with the period being determined by theworst case. Therefore, it is customary for the maximum time betweenrefresh operations in a DRAM device to be not greater than the minimumperiod over which a high charge level may be expected to remainreadable, even though cells storing low charge levels may be expected toremain readable for a longer period.

In a method according to an embodiment of the present invention, aperiod of readability for a high charge level is increased. In anapparatus according to one embodiment of the invention, a bias circuitis configured to reduce a difference between the period of readabilityfor the high charge level and the period of readability for the lowcharge level.

FIG. 8 shows a device including a bias circuit 140 a according to anembodiment of the invention. Bias circuit 140 a includes a biascapacitor BC1, having one end connected to bitline BL1 and the other endconnected to an active-low bias signal B1, and a bias capacitor BC2,having one end connected to bitline BL2 and the other end connected toan active-low bias signal B2. As shown in FIG. 8, bias capacitors BC1,BC2 may each be fabricated as an NMOS FET with the source and drainshorted together. In other implementations, bias capacitors BC1, BC2 maybe fabricated as two-terminal capacitors (e.g. trench capacitors).

In an exemplary implementation, bias capacitors BC1, BC2 are fabricatedas low-V_(t) NMOS FETs. One possible advantage that may be realized inimplementing a bias capacitor as a MOSFET is to minimize the amount ofcapacitance that the bias capacitor adds to the bitline. Other possibleadvantages to a device as shown in FIG. 8 may include ease ofincorporation into existing processes, e.g. in terms of added processdifficulty and required degree of circuit redesign. However, suchadvantages are not essential to the practice of the invention.

FIG. 9 shows a timing diagram of a device as shown in FIG. 8 in a casewhere a high data value is read from a cell on bitline BL1. After theprecharges on the bitlines have been equalized, and before the senseamplifier is enabled, the bias signal corresponding to the referencebitline (here, bias signal B2 corresponding to bitline BL2) is pulledlow. As a result, the voltage on bitline BL2 drops below Vblp by anamount ΔV_(BIAS), and the voltage difference between the bitlines isincreased from ΔV to ΔV_(H) (where ΔV_(H=ΔV+ΔV) _(BIAS)). Although FIG.9 shows that bias signal B2 is pulled low after activation of wordlineWL, in another implementation bias signal B2 may be pulled low beforeand/or during activation of wordline WL.

FIG. 10 shows a timing diagram of a device as shown in FIG. 8 in a casewhere a low data value is read from a cell on bitline BL1. In this caseas well, after the precharges on the bitlines have been equalized, andbefore the sense amplifier is enabled, the bias signal corresponding tothe reference bitline (here, bias signal B2 corresponding to bitlineBL2) is pulled low. As a result, the voltage on bitline BL2 drops belowVblp by a voltage change ΔV_(BIAS), and the voltage difference betweenthe bitlines is reduced from ΔV to ΔV_(L) (where ΔV_(L)=ΔV−ΔV_(BIAS)).As noted above, in another implementation bias signal B2 may be pulledlow before and/or during activation of wordline WL. It may be desirableto choose a magnitude of ΔV_(BIAS) such that the voltage differenceΔV_(L) will not fall below a sense margin of the sense amplifier.

In existing DRAM devices, it is typical for one instance of circuitrysuch as a sense amplifier and a precharge circuit to be shared amongmore than one cell array. In a device according to a further embodimentof the invention, one instance of bias circuit 140 may also be sharedamong more than one cell array 110. Such an arrangement may includecircuits to isolate the array or arrays not being read. FIG. 11 shows ablock diagram of a device according to an embodiment of the inventionthat includes two cell arrays 110L, 110R and isolation circuits 150L,150R. FIG. 12 shows a block diagram of an exemplary implementation ofcell arrays 110L, 110R suitable for use in a device as shown in FIG. 11,with cells 1–4 each comprising a respective one of FETs M1–4 and arespective one of cell capacitors C1–4.

FIG. 13 shows a schematic diagram of an isolation circuit 150 a suitablefor use in a device as shown in FIG. 11. Isolation circuit 150 aincludes two N-channel FETs I1, I2, with the source-drain circuit ofeach FET being series-connected to a respective one of the bitlines BL1,BL2 and the gates of the two FETs being connected to an isolation signalI. In other implementations, P-channel devices may be used instead of(or in addition to) the N-channel devices of an isolation circuit asshown in FIG. 13, with a corresponding change as appropriate in thepolarity and/or value of isolation signal I.

FIG. 14 shows a timing diagram of a device as shown in FIG. 13 in a casewhere a high data value is read from cell 1 of cell array 110L. Uponactivation of precharge control signal P, isolation signal IL ofisolation circuit 150L is raised to an increased voltage level Vpp toselect cell array 110L, and isolation signal IR of isolation circuit150R is lowered to Vss to isolate cell array 110R. In anotherimplementation, isolation signals IL, IR may be activated beforeprecharging. Sensing of the charge level stored in the cell proceeds asdescribed above.

In other implementations of a device as shown in FIG. 11, the seriesconnection of sense amplifier 120, precharge circuit 130, and biascircuit 140 along bitlines BL1, BL2 may occur in any order. AlthoughFIG. 11 shows cell arrays 110L and 110R being coupled to differentwordlines, in another implementation the timing as shown in FIG. 14 maybe varied to support reading different data values from arrays 110L and110R for the same word.

It may be desirable to bias down a bitline that provides a referencepotential rather than to bias down a bitline that shares charge.(Instead of, or in addition to, biasing down a bitline that provides areference potential, it may be desirable in another application to biasup a bitline that shares charge.) A method according to a furtherembodiment of the invention includes selecting a bitline to be biased.

FIG. 11 shows a device in which two wordlines are coupled to eachbitline. Specifically, wordlines WL1 and WL3 are coupled to bitline BL1,and wordlines WL2 and WL4 are coupled to bitline BL2. In practice, sucha structure may be expanded such that many wordlines are coupled to eachbitline. In a typical DRAM device, for example, 256 or 512 wordlines maybe coupled to each bitline. (These wordlines may also be coupled toother bitlines that are connected to other cell arrays.) With respect tothe two bitlines BL1 and BL2 that are connected to the cell arrays 110Land 110R, each wordline is coupled to one and only one of these twobitlines. Therefore, the (possibly many) wordlines coupled to thebitlines of the cell arrays are divided into two nonoverlapping sets:wordlines coupled to bitline BL1, and wordlines coupled to bitline BL2.

When a wordline is selected, the corresponding cell is activated andcharge sharing occurs on the corresponding bitline. In an apparatus ormethod according to a further embodiment of the invention, selection ofa wordline is used to identify the bitline to be biased. In the exampleof a device as shown in FIG. 11, if wordline WL2 or wordline WL4 isselected, then bitline BL1 is biased down, and if wordline WL1 orwordline WL3 is selected, then bitline BL2 is biased down.

The foregoing presentation of the described embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments are possible, andthe generic principles of utilizing a biasing circuit within a memorydevice presented herein may be applied to other embodiments as well. Forexample, embodiments of the invention may be implemented in part or inwhole as a hard-wired circuit or as a circuit configuration fabricatedinto an application-specific integrated circuit. A device according toan embodiment of the invention may also be fabricated including one ormore DRAM cell designs as are known in the art other than theone-transistor cell shown in FIG. 1: for example, a three-transistor(3T) cell design.

A device according to an embodiment of the invention as described hereinmay be used in several different DRAM implementations, includingsynchronous DRAM (SDRAM), double data rate DRAM (DDR DRAM), and RambusDRAM (RDRAM). Methods according to embodiments of the invention may alsobe practiced in DRAM devices for storage of non-binary data values (i.e.data values indicating more than two levels). Principles of theinvention may also be applied to embedded DRAM products such as embeddedgraphics controllers. Thus, the present invention is not intended to belimited to the embodiments shown above but rather is to be accorded thewidest scope consistent with the principles and novel features disclosedin any fashion herein.

1. A method of data access, said method comprising: precharging a firstbitline and a second bitline to a precharge voltage; permitting chargesharing between a capacitance of a memory cell and one of the prechargedfirst bitline and the precharged second bitline; biasing the other ofthe precharged first bitline and the precharged second bitline todecrease a voltage level of the biased bitline below the prechargevoltage in order to increase a refresh period; and subsequent to saidpermitting charge sharing and said biasing, sensing a difference betweena potential of the first bitline and a potential of the second bitline.2. The method according to claim 1, wherein sensing the differencebetween a potential of the first bitline and a potential of the secondbitline includes amplifying said difference.
 3. The method according toclaim 1, wherein said permitting charge sharing includes applying apotential to a gate of a transistor of the memory cell.
 4. The methodaccording to claim 1, wherein said biasing includes applying a potentialto a bias capacitor coupled to the the other of the precharged firstbitline and the precharged second bitline.
 5. A method of data access,said method comprising: selecting a wordline to perform charge sharingbetween a memory cell and a bitline coupled to the wordline; asserting abias signal corresponding to the wordline for decreasing a potential ofa reference bitline; and sensing a difference between a potential of thebitline coupled to the wordline and the decreased potential of thereference bitline.
 6. The method according to claim 5, wherein saidasserting the bias signal occurs subsequent to said selecting awordline.
 7. The method according to claim 5, wherein said sensing thedifference includes sensing a difference between the potential of thebitline and the altered potential of the reference bitline.
 8. A methodof data access, said method comprising: precharging a first bitline anda second bitline to a precharge voltage; permitting charge sharingbetween a capacitance of a memory cell and the precharged first bitline;biasing a selected one of the precharged bitlines to decrease a voltagelevel of the biased bitline below the precharge voltage so as toincrease a refresh period; and subsequent to said permitting chargesharing and said biasing, sensing a difference between a potential ofthe first bitline and a potential of the second bitline.
 9. The methodaccording to claim 8, wherein said biasing includes applying a potentialto a bias capacitor coupled to the selected bitline.
 10. A semiconductormemory device comprising: a precharging circuit configured and arrangedto precharge an active bitline and a reference bitline; a memory cellconfigured and arranged to share charge with the active bitline; a biascircuit configured and arranged to decrease a potential of the referencebitline to increase a refresh period in a semiconductor memory device;and a sense amplifier configured and arranged to sense a differencebetween a potential of the active bitline and a potential of thereference bitline.
 11. The semiconductor memory device according toclaim 10, wherein the memory cell includes a field-effect transistor anda capacitor.
 12. The semiconductor memory device according to claim 10,wherein the memory cell is coupled to a wordline and is furtherconfigured and arranged to share charge with the active bitline upon apredetermined alteration in a potential of the wordline.
 13. Thesemiconductor memory device according to claim 10, wherein the biascircuit includes a bias capacitor coupled to the reference bitline. 14.The semiconductor memory device according to claim 13, wherein the biascapacitor includes a metal-oxide-semiconductor field-effect transistorhaving a low threshold voltage.
 15. The semiconductor memory deviceaccording to claim 14, wherein a magnitude of the threshold voltage ofthe metal-oxide-semiconductor field-effect transistor is less than threehundred millivolts.
 16. The semiconductor memory device according toclaim 13, wherein the bias capacitor includes an n-channelmetal-oxide-semiconductor field-effect transistor having a low thresholdvoltage.
 17. The semiconductor memory device according to claim 16,wherein a magnitude of the threshold voltage of themetal-oxide-semiconductor field-effect transistor is less than threehundred millivolts.
 18. The semiconductor memory device according toclaim 10, further comprising: a second memory cell configured andarranged to share charge with the active bitline; a first isolationcircuit configured and arranged to isolate the memory cell from thesense amplifier; and a second isolation circuit configured and arrangedto isolate the second memory cell from the sense amplifier.